| 摘要 |
<p>According to an embodiment of the invention, a parallel SC ADC (switched capacitor analogue-to-digital converter) is provided, comprising a passive sampling technique controlled by a global clock phase (ζ) to reduce the influence of the sampling phase skew. Since it does not require operational amplifiers for sampling, it is very suitable for high speed applications, and yet it can reduce the sampling-phase-skew-related distortion by 20-40dB in a high speed, parallel SC ADC.</p> |
