SILICON-ON-INSULATOR CONFIGURATION WHICH IS COMPATIBLE WITH BULK CMOS ARCHITECTURE

摘要

A method for creating a SOI CMOS type device compatible with bulk CMOS using a bulk CMOS physical layout database. The method uses the P-well and N-well masks used in fabrication of bulk CMOS devices. The N-well and P-well regions are fabricated by implanting the appropriate dopants above and below the buried oxide layer to create the basic SOI CMOS structure. Particular modifications to the basic SOI CMOS structure include providing a mask for establishing ohmic contact with the wells below the buried oxide layer. The modification uses a separate mask which is generated from the existing bulk CMOS mask database. The mask is generated by doing the following logical AND and OR functions on the existing CMOS layers: a) SOURCE/DRAIN [AND] P<+> [AND] P-WELL [AND] 1st CONTACT; b) SOURCE/DRAIN [AND] N<+> [AND] N-WELL [AND] 1st CONTACT; c) a) [OR] b).