发明名称 |
Variable equilibrate voltage circuit for paired digit lines |
摘要 |
A method and circuit for rapidly equilibrating paired digit lines of a memory array of a dynamic random access memory device is described. The equilibrate circuit includes a bias-circuit coupled to sense amplifier circuitry for adjusting the equilibrate voltage during testing. A method is described for testing memory cell margin by adjusting the equilibrate voltage until an error is detected. The bias circuit is described as a pull-up transistor coupled to a common mode of a cross-coupled n-sense amplifier.
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申请公布号 |
US5903502(A) |
申请公布日期 |
1999.05.11 |
申请号 |
US19970977757 |
申请日期 |
1997.11.25 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
PORTER, STEPHEN R. |
分类号 |
G11C7/12;G11C11/4094;G11C29/02;G11C29/50;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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