Ultra low jitter differential to fullswing BiCMOS comparator with equal rise/fall time and complementary outputs

摘要

A pair of complementary signals are switched between a high state and a low state such that the complementary signals are switched within a time period less than two gate delays. An inverter biases other inverters so that these two inverters are maintained at their threshold levels. The maintenance at the threshold values enable these two inverters to be switched quickly.