| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a high performance SDRAM by providing/integrating a logic block generating a row address strobe signal, a column address strobe signal and a write-in enable signal and a memory block independently controlled in response to those signals in one chip. SOLUTION: The logic block 400 and the memory block 300 are connected by many paths. Activation, read-out operation and precharge operation of an A bank 303 are controlled independently by the row address strobe signal/RASa, the column address strobe signal/CASa and the write-in enable signal/WEa, and similar operation of a B bank 305 are controlled independently by the row address strobe signal/RASb, the column address strobe signal/CASb and the write-in enable signal/WEb. The address data and the input/output data are multiplexed. Since a command is applied to the B bank 305 while the A bank 303 command executes, the performance is improved.</p> |
