DATA OUTPUT SYNCHRONOUS CLOCK GENERATOR

摘要

PROBLEM TO BE SOLVED: To provide a data output synchronous clock generator which supplies a clock that has a little attenuation of a signal and is synchronized with many devices. SOLUTION: A data clock which is generated by an synchronous DRAM device 14d that is arranged at the farthest end from a memory controller 12 is synchronizes with a command clock that is sent from a clock generator 11 to a command clock signal line 21a and is supplied front an output pin 22d to synchronous DRAM devices 14a to 14d through a data clock outputting signal line 23a. Data which are outputted from each of the devices 14a to 14d are synchronized with the data clock, transmitted through a data bus 25 from data input-output lines 24a to 24d in the same direction of the data clock and sent to the controller 12.