发明名称 PLL FREQUENCY SYNTHESIZER
摘要 PROBLEM TO BE SOLVED: To make C/N high and to reduce a reference leak by without making a settling time long at all channel frequencies by making the output variable voltage of a charge pump circuit variable. SOLUTION: At the time of phase acquisition, a transistor 30a is controlled with the signal outputted at the terminal UPa of a phase comparator 2 and a transistor 30b is controlled with the signal outputted at the terminal UPb of a NAND gate 21, so that a flow of a current determined by a constant current source 31 to the output A is determined. A transistor 33a is controlled with the signal outputted to the terminal DOWNa of the phase comparator 2 and a transistor 33b is controlled with the signal outputted to the terminal DOWNb of an AND gate 22, so that a flow of the current determined by a constant current 32 from the output A is determined. Switching transistors 30b and 33b of the charge pump circuit 3 become small in ON resistance and the output variable voltage range becomes wide.
申请公布号 JPH10313248(A) 申请公布日期 1998.11.24
申请号 JP19970122287 申请日期 1997.05.13
申请人 NEC CORP 发明人 ADACHI MASAHIRO
分类号 H03L7/18;H03L7/093;H03L7/107 主分类号 H03L7/18
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