发明名称 Verfahren zur Herstellung eines vertikalen MOS-Transistors
摘要 In order to produce a vertical MOS transistor, a mask (13) with an opening is formed on a semiconductor substrate. Grown in the opening by selective epitaxy is a layer sequence (14) comprising a lower source/drain region (141), a channel region (142) and an upper source/drain region (143). Facets are formed at the edge such that the layers are thinner at the edge than in the centre. A gate dielectric (16) and gate electrode are formed at the edge of the layer sequence.
申请公布号 DE19711481(A1) 申请公布日期 1998.10.08
申请号 DE19971011481 申请日期 1997.03.19
申请人 SIEMENS AG, 80333 MUENCHEN, DE;FORSCHUNGSZENTRUM JUELICH GMBH, 52428 JUELICH, DE;RUHR-UNIVERSITAET BOCHUM, 44801 BOCHUM, DE 发明人 AEUGLE, THOMAS, DR.RER.NAT., 81735 MUENCHEN, DE;ROESNER, WOLFGANG, DR.RER.NAT., 81739 MUENCHEN, DE;BEHAMMER, DAG, DIPL.-PHYS., 42855 REMSCHEID, DE;VESCAN, LILI, 52072 AACHEN, DE
分类号 H01L21/336;H01L29/78;(IPC1-7):H01L21/336 主分类号 H01L21/336
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