A shift register useful as a select line scanner for a liquid crystal display

摘要

The shift register includes cascaded stages, each having an output transistor responding to one of several phase shifted clock signals, and an input transistor switch which responds to an output pulse of an upstream stage in the cascaded stage chain, in response to another phase-shifted clock signal. The input transistor develops a control signal which charges a capacitance associated with a control electrode of a switched pull-up output transistor. The capacitance voltage causes the output transistor to generate an output pulse when a subsequent clock pulse is input to the output transistor. A clamping transistor discharges the capacitance to prevent additional output pulses when further clock signal pulses occur. The clamping transistor responds to an output pulse of a downstream stage. After the output transistor control signal is clamped, the clamping transistor develops an impedance in the output transistor control electrode which is higher than when the signal is clamped. Pref. the capacitance is formed between the output transistor electrodes. The stage may include a non-switched pull-down transistor.