发明名称 |
Self test of core with unpredictable latency |
摘要 |
A test method and means for in integrated circuit (10) having asynchronous communication capabilities including a transmitter (12) and a receiver (14). A pattern generator (24) is provided for generating patterns directly from within the integrated circuit (10). In the best presently known embodiment, a serializer (16) provides a serial output (20) and a deserializer (18) processes a serial input (22) into a parallel signal and provides the parallel signal to a receiver (14). The pattern generator (24) is preprogrammed to provide a parallel data pattern which can optionally and intermittently be provided to the transmitter (12) in a test mode (44). In the test mode (44), signal is routed from the serializer (16) directly to the deserializer (18) via an external loop back path (34) or an internal alternative loop back path (34a). When in the test mode, comparison unit (38) internally generates a pattern identical to that produced by the pattern generator (24) and locks onto signal received from the receiver (14) to perform a functional test (54) and an optional parametric test (58). |
申请公布号 |
US5790563(A) |
申请公布日期 |
1998.08.04 |
申请号 |
US19970879673 |
申请日期 |
1997.06.23 |
申请人 |
LSI LOGIC CORP. |
发明人 |
RAMAMURTHY, KRISHNAN;PAN, RONG;DUCAROIR, FRANCOIS |
分类号 |
G01R31/317;G01R31/3181;G01R31/3185;(IPC1-7):G06F11/00 |
主分类号 |
G01R31/317 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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