发明名称 COMMON BUFFER TYPE SWITCH PART
摘要 <p>PROBLEM TO BE SOLVED: To reduce the memory capacity by constituting a used and an idle address storage memory as one memory. SOLUTION: A buffer memory 11 stores input data 101 in a current write address 102 and reads the stored data out of a current read address 107 as output data 106. A write register 14-1 holds the current write address and a read register 15-1 holes the current read address. An address storage memory 112 has a used address area wherein addresses used by the buffer memory 11 are held and an idle address area where addresses which are not used by the buffer memory 11 are held in a state varying with the time. A memory control means controls the writing and reading of the address storage memory 12 so that the used addresses are held in the used address area and the idle addresses are held in the idle address area.</p>
申请公布号 JPH10190684(A) 申请公布日期 1998.07.21
申请号 JP19960350387 申请日期 1996.12.27
申请人 NEC ENG LTD 发明人 SHIMOMURA NOBUFUMI
分类号 H04Q3/00;H04L12/28;(IPC1-7):H04L12/28 主分类号 H04Q3/00
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