| 摘要 |
PROBLEM TO BE SOLVED: To shorten test time by executing boundary scan and internal scan in a common procedure in parallel. SOLUTION: A scan tap control circuit is provided with TDI, TRS, TDO, TMS, TCK terminals necessary for boundary scan. A scan tap control circuit has clock FF 111 and 112 supplying respectively clock signals from a tap controller 101 and sends clock signals for internal testing SCK1 and SCK2 by way of an AND circuit 113 and an OR circuit 114. The state of the scan tap control circuit is controlled with a test mode signal given to the TMS terminal to perform boundary scan. Also, signals TS, SMC, S1, SO, SCK1, SCK2 necessary for internal scan can be output and the internal scan can be done by using the procedure as it is. In this manner, test time is shortened and thus, economy can be improved. |
