发明名称 Method of manufacturing a semiconductor device having multi-layered wiring without hillocks
摘要 An Al alloy interconnection layer is deposited on a silicon oxide layer, and a first carbon layer is formed on the Al alloy interconnection layer. Then, the first carbon layer and the Al alloy interconnection layer are patterned, thereby forming a first interconnection layer consisting of the Al alloy interconnection layer and the first carbon layer. Sequentially, a second carbon layer is formed on the first interconnection layer and the silicon oxide layer. The second carbon layer is entirely etched by the RIE method, thereby leaving the second carbon layer only on side surfaces of the first interconnection layer. A high temperature layer made of SiO2 is deposited on the second carbon layer, the first interconnection layer and the silicon oxide layer. Thereafter, the high temperature layer is etched back until the first carbon layer is exposed, thus being flattened. An interlayer insulating layer is deposited on the high temperature layer and the first interconnection layer.
申请公布号 US5759912(A) 申请公布日期 1998.06.02
申请号 US19960653904 申请日期 1996.05.28
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 MORI, KAZUYA;OTSUKA, KENICHI
分类号 H01L21/3205;H01L21/768;H01L23/52;(IPC1-7):H01L21/476 主分类号 H01L21/3205
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