发明名称 L-CONNECT ROUTING OF DIE SURFACE PADS TO THE DIE EDGE FOR STACKING IN A 3D ARRAY
摘要 Integrated circuit chips and method of routing the interface pads (12) from the face of the chip or die to one or more sidewall surfaces of the die. The interconnection (14) is routed from the face of the die (11) to one or more edges of the die, then routed over the edge of the die and onto the side surface. A new pad (17) is then formed on the sidewall surface, which allows multiple die or chips to be stacked in a three-dimensional array, while enabling follow-on signal routing from the sidewall pads. The routing of the interconnects and formation of the sidewall pads can be carried out in an L-connect or L-shaped routing configuration, using a metalization process such as laser pantography.
申请公布号 WO9818160(A1) 申请公布日期 1998.04.30
申请号 WO1997US19053 申请日期 1997.10.17
申请人 THE REGENTS OF THE UNIVERSITY OF CALIFORNIA 发明人 PETERSEN, ROBERT, W.
分类号 H01L25/065;(IPC1-7):H01L21/44;H01L21/60;H01L21/56 主分类号 H01L25/065
代理机构 代理人
主权项
地址