A secure processor arrangement for a communications secure kernel of a secure processor system. This processor arrangement provides protection of plain text data and suitable isolation of data necessary to support single processor (1) architecture. A red memory subsystem (2,4) stores plain text data and a black memory subsystem (3,5) stores cypher text data. In order to prevent mishandling of plain text data, the single processor (1) is allowed to directly read and to write red memory (4), but the single processor (1) is only permitted to directly read from the black memory (5).
申请公布号
DE69031014(T2)
申请公布日期
1998.04.02
申请号
DE1990631014T
申请日期
1990.09.11
申请人
MOTOROLA, INC., SCHAUMBURG, ILL., US
发明人
MARINO, JOSEPH THOMAS, JR., FOUNTAIN HILLS, ARIZONA 85268, US;CORE, RONALD SCOTT, GLENDALE, ARIZONA 85308, US