| 摘要 |
A data receiving device, applicable to a system which receives data sequentially transmitted thereto in a non-periodical manner under control of a host CPU, is configured by a receiving circuit, a counter circuit, a memory circuit and register circuits. A plurality of input data are sequentially supplied to the receiving circuit, so that the receiving circuit produces a strobe signal when receiving each input data. The counter circuit measures a receiving interval of time between moments of receiving two input data which are consecutively received by the receiving circuit. The memory circuit has specific storage capacity for storing predetermined sets of main data and time data, wherein the main data are extracted from the receiving circuit and the time data correspond to the receiving interval of time. Herein, the main data are stored with being related to the time data. If the storage capacity of the memory circuit is fully occupied by the predetermined sets of main data and time data, the memory circuit is put in a read state, so that the main data and time data are transferred to the register circuits in turn. The host CPU controls output timings by which the main data and time data are respectively outputted from the register circuits, so that the system can receive the main data together with the time data in a desired manner.
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