Clock circuit for reading a multilevel non volatile memory cells device

摘要

A timing circuit for reading from a device comprising multi-level non-volatile memory cells, which circuit comprises a single programmable delay block (RC) connected to an input terminal (ATD) for memory address line transition signals. The delay block drives a counter (CONT) which feedback controls the control block through a combinational logic circuit (COMB_SCA) connected to the output terminal (OUT_RC) of the programmable delay block. A logic output circuit (COMB_OUT), connected to the output terminal of the delay block and to the counter, generates the timing signals (OUT). <IMAGE>