| 摘要 |
<p>An architecture and memory mapping technique for an extended multiprocessor (XMP) computer system are provided to overcome physical/electrical limitations of single bus architecture while maximizing bus bandwidth utilization. The XMP computer system includes multiple SMP nodes each including an XMP interface and a repeater structure. The SMP nodes are connected to each other by unidirectional point-to-point links. The repeater structure in each SMP node includes an upper level bus coupled to one or more transaction repeaters. Each transaction repeater broadcasts transactions to bus devices attached to separate lower level buses. Transactions originating in a particular SMP node are stored in a queue, whereas transactions originating in other SMP nodes bypass the incoming queue to the bus device. Multiple transactions may be simultaneously broadcast across the point-to-point link connections between the SMP nodes in a defined, uniform order. Each of the n SMP nodes is assigned 1/n of the total address space. Cache coherency information is stored for the memory in each SMP node. Memory regions may be assigned to operate in one of three modes: normal, migratory, or replicate. When operating in normal mode, transaction to an address space assigned to a particular node are tried only locally in that node first. In migratory mode transactions are always sent globally. And in replicate mode duplicate copies of the replicate memory region are assigned to each SMP node so that transactions are always tried locally first, and only sent globally if an improper cache coherency state is returned. <IMAGE></p> |
