发明名称 PHASE-LOCKED LOOP FOR IMPROVING PHASE-SYNCHRONIZING TIME
摘要 <p>PROBLEM TO BE SOLVED: To obtain synchronization in an early stage by reducing the deviation of a voltage-controlled oscillator due to the variation of the surrounding environment. SOLUTION: A switch (SW) 108 is turned off before starting communication. The data read out from the memory of a second buffer 110 are inputted to a VCO 104 through a D/A converter 111 and an adder 112 and a specific frequency fVCO is outputted from the VCO 104. The frequency fVCO is also supplied to a variable frequency divider 105 which divides the frequency fVCO under the control of a second controller 106 and a phase comparator 102 compares the divided frequency with an input from a reference signal generator 101. The result of the comparison is supplied to the SW 108 and a level detector 113 which compares the result with a reference level through a LPF 103 and inputted to a control section 107. The section 107 discriminates the phase advancing or delaying state of a reference signal and controls the phase of the VCO 104 by increasing or decreasing the data in the buffer 110 in accordance with the discriminated result. When the phase of the VCO 104 is controlled, the section 107 stores the data in the buffer 110 in a first buffer 109. When communication is started, the data are read out from the buffer 109 and the SW 108 is turned on, resulting in a steady state.</p>
申请公布号 JPH09331253(A) 申请公布日期 1997.12.22
申请号 JP19960349362 申请日期 1996.12.27
申请人 SAMSUNG ELECTRON CO LTD 发明人 BOKU ZAIZEN
分类号 H03L7/08;H03L7/10;H03L7/189;(IPC1-7):H03L7/10 主分类号 H03L7/08
代理机构 代理人
主权项
地址