SEMICONDUCTOR INTEGRATED CIRCUIT AND OPTICAL SIGNAL RECEIVER

摘要

PROBLEM TO BE SOLVED: To adjust the phase of a clock signal to an optimum phase automatically by sampling data respectively at a phase lead point by a prescribed phase from a clock timing and at a phase lag point by a prescribed phase and comparing the results so as to change the absolute phase. SOLUTION: A clock signal CLK3 received via an input terminal P2 is fed to an FF 11 via a phase adjustment circuit 12. Furthermore, a data signal ED3 whose phase is to be compared with the phase of the signal CLK 3 is given to the circuit 12 as a signal ED3' via a data input buffer circuit 13. The FF 11 fetches data when a clock signal CK is in crossing with a center potential on the way of changing itself from an H to an L level as a sampling timing. Then the data fetched by the FF 11 are outputted as a signal ED3 from a data output buffer circuit 15. The circuit 12 compares the phase of the received data signal with the phase of the clock signal and provides the clock signal CK whose phase is adjusted to an optimum phase to the FF 11.