Architecture of a system of array processors with multiple parallel structures

摘要

The processor system is arranged on a board to form a group of nodes(1a-1d) for SIMD operation. Each node has a number of elementary processors(3) connected to each other so as to form a ring of elementary processors(2). Each elementary processor(2) being associated with a connection cell(7a) connected to the cells of neighbouring elementary processors so as to form a ring network(4). Each SIMD node is fitted with an addressing and memory module(11) which ensures independent addressing of each node. In addition each SIMD node has a control unit(9) connected to neighbouring node control units so as to form a inter-node control network(6) in which circulates priority tokens. Each addressing and memory module of a node being connected to a neighbouring nodes so as to form an inter-node data network(8).