发明名称 Dual-port data cache memory
摘要 A dual-port data cache is provided having one port dedicated to servicing a local processor and a second port dedicated to servicing a system. The dual-port data cache is also capable of a high speed transfer of a line or lines of entries by placing the dual-port data cache in "burst mode." Burst mode may be utilized with either a read or a write operation. An initial address is latched internally, and a word line in the memory array is activated during the entire data transfer. A control circuit is utilized to cycle through and access a number of column addresses without having to provide a separate address for each operation.
申请公布号 US5590307(A) 申请公布日期 1996.12.31
申请号 US19930000711 申请日期 1993.01.05
申请人 SGS-THOMSON MICROELECTRONICS, INC. 发明人 MCCLURE, DAVID C.
分类号 G06F12/08;G11C8/16;G11C11/401;G11C11/41;(IPC1-7):G06F12/08 主分类号 G06F12/08
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