| 摘要 |
PURPOSE: To attain the conversion of a sampling frequency completely with digital processing without depending on analog converting processing. CONSTITUTION: A digital signal Sin (α) sampling an analog signal is inputted synchronously with a clock signal at a frequency α and the sample point of this analog signal is seemingly increased and converted into a frequency βhigher than the frequency α. Then, this device is provided with a clock converting part 100 for outputting a digital signal Cin (β), for which this sampling points are increased, synchronously with a clock signal at the frequency βand a phase correction part 10 for correcting the signal level of the seemingly increased digital signal Cin (β) caused by the phase deviation of the sampling point approximately to the signal level of the sampling point of the analog signal. |
