发明名称 CIRCUIT AND METHOD OF PREDICTIVE ENCODER/DECODER MADE INTO PIPELINE TIME-WISE
摘要 PROBLEM TO BE SOLVED: To provide video circuit and method using the stagger array of the processors of predictive encoders and decoders. SOLUTION: A pipelined prediction encoder/decoder circuit 1 for encoding or decoding input signals S1 received by a specified frame rate and turning them to the output signals S0 of the same frame rate adopts the plural N pieces of the predictive encoders 10. An input buffer 13 used for extracting the information of the respective data frames of the input signals S1 and supplying it to the corresponding encoders/decoders at the rate of 1/N fold. Other than providing digitized frame information to the encoder/decoder processing the next received image frame, the respective encoders/decoders generate corresponding encoded/decoded information every time it is received. The encoded/decoded information is provided to a corresponding frame buffer 15, is connected to a multiplexer 25 further and forms encoded/decoded output S0 .
申请公布号 JPH08265164(A) 申请公布日期 1996.10.11
申请号 JP19950338414 申请日期 1995.12.26
申请人 AT & T CORP 发明人 NERUSON BOTSUTSUFUOODO SAADO;JIYOOJI JIYON KUSUTOKA;JIYON NOOMAN MEIRUHOTSUTO
分类号 H04N7/32;H03M7/36;H04N7/26;H04N7/50;(IPC1-7):H03M7/36 主分类号 H04N7/32
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