| 摘要 |
The circuit provides a demodulator to eliminate the need for clock recovery and includes an input filter, the 1st, 2nd low pass filter, the 1st, 2nd A/D converter, an intermediate buffer memory compensating the time difference between read and write, a reference wave form memory, a time synchronizer detecting each location of the data by calculating correlations between modulated signals and the reference wave forms, an input phase determinater, a differential phase detection and binary data determinater, a parallel/serial converter.
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