| 摘要 |
A method and system for coupling a coprocessor (220) to a master device, in which the coprocessor (220) emulates a memory interface to the master device, like that of a memory device. The coprocessor (220) is coupled to a memory bus (212) and receives memory accesses directed to a set of addresses not covered by memory devices also coupled to the memory bus (212). The coprocessor (220) is disposed to receive data written from the master device, perform a function on that data, and respond to a read data command from the master device with processing results. The coprocessor (220) uses memory block transfers to read data from and write data to memory devices also coupled to the memory bus (212). The coprocessor (220) is adapted to compute, in response to data written to it by the graphics processor, a graphical function such as 3D processing function, MPEG video compression or decompression, a raytracing function, or some related function in support of graphics processing. The coprocessor (220) may communicate with the central processor (201) and its memory (202) using a memory access operation performed by the central processor (201), and may communicate with the graphics memory (211) using a memory block transfer performed by the graphics processor (210).
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