| 摘要 |
PCT No. PCT/DE94/01113 Sec. 371 Date Mar. 27, 1996 Sec. 102(e) Date Mar. 27, 1996 PCT Filed Sep. 23, 1994 PCT Pub. No. WO95/09404 PCT Pub. Date Apr. 6, 1995A processor is disclosed, in which a block memory (ADM), a search domain memory (SDM), a two-dimensional processor/memory cell field (PRA) and a control unit (CTRL) are preferably monolithically integrated in a semiconductor chip. The word width of toe search domain memory (SDM) is organised so that the processor/register cell field (PRA) is supplied, in parallel per system cycle (CLK) with data (SF) on picture elements of a new complete column of the search domain. At the same time, a control sequence is stored in the control unit (CTRL). The control sequence supplies data flow control signals (DFC) and addresses (ADR1, ADR2) to the block memory and search domain memory in parallel, per system cycle. The control unit essentially consists of a shift register into which external control signals (CD) of any desired control sequences may be written. An essential advantage of the invention is that it allows a comparatively high hardware utilisation even in the case of block matching algorithms based on an incomplete search. |
