| 摘要 |
A SRAM testing circuit utilized to assure that a voltage is at a sufficient level for accessing a memory cell including a pair of memory cells each including those elements necessary to duplicate the memory cells of an associated memory array, a circuit for providing alternating-valued input signals for writing to the pair of memory cells during each clock period at which a write operation may occur, apparatus for emulating the load provided to a bitline of an associated memory array, apparatus for applying the input signals to one of the pair of memory cells and applying the inverse of the input signals to the other of the pair of memory cells, apparatus for testing both the condition of each of the memory cells after the application of the input and inverse input signals against the condition of the signals provided to each of the cells to determine if each of the pair of memory cells has switched to the appropriate condition, and apparatus for generating a fail signal if either one of the pair of memory cells has not switched to the appropriate condition. |
