发明名称 |
FRAME SYNCHRONIZING DEVICE |
摘要 |
PURPOSE: To realize the frame synchronization device to demultiplex a time division multiplex signal in parallel from an STM-4C structure of a broad band overall information communication network in compliance with the ITU-T recommendations. CONSTITUTION: A serial parallel conversion circuit 10 and a byte arrangement circuit 30 detect a frame byte from high speed reception data at a transmission rate of 622 Mbps, align bytes based on a detected time and provides an output of frame data as 8-bit parallel data. A synchronizing signal pattern detection circuit 90 and a consecutive pattern confirmation circuit 100 detect frame bytes continuously based on a low speed clock obtained by applying 8 frequency division from an original clock signal at a frequency divider circuit 70 to seek a frame synchronizing signal. As a result, the power consumption is reduced and the amount of the hardware is decreased. |
申请公布号 |
JPH08163116(A) |
申请公布日期 |
1996.06.21 |
申请号 |
JP19940316450 |
申请日期 |
1994.12.20 |
申请人 |
KANKOKU DENSHI TSUSHIN KENKYUSHO;KANKOKU DENKI TSUSHIN KOUSHIYA |
发明人 |
JIYO SEIIKU;KIN HOSHIMICHI;TEI KIHAN;SOU GENTETSU;RI KUNFUKU |
分类号 |
H04M7/08;H04J3/00;H04J3/06;H04L7/08 |
主分类号 |
H04M7/08 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|