| 摘要 |
<p>PURPOSE: To supply a count completion signal with cycles similar to that of a normal operation mode to a microcomputer even in a low power consumption mode wherein the frequency of a clock is lowered. CONSTITUTION: An n-bit counter 50 repeatedly counts down with data P and an initial value supplied by a reload register 20 and sends out the count completion signal INT in sequence. A decision circuit 60 detects the mode of a system and supplies control signals EN0 and EN1 corresponding to the detection result to the counter 50. When the detection result is the low power consumption mode, the least significant digit bit in the counter 50 is inhibited from being counted with the control signals EN0 and EN1 and the counting operation of only the high-order bits is performed. Consequently, the generation period of the count completion signal INT is equal to that of the normal operation mode.</p> |
