Vertikal partitionierter, primärer Befehls-Cache-Speicher

摘要

An instruction cache (10) with separate storage cells for sequence control data is disclosed. Instructions are decoded (8) prior to being stored in the instruction cache which serves a primary cache, while prior hierarchical levels of memory store instructions in m an encoded form. Because the instructions have a variable-length, the instruction cache includes a next address determination circuit (30) to determine the next instruction address. The sequence control data enables a next instruction address to be generated during a fetch stage for a current instruction, thereby avoiding the need for an otherwise necessary additional decoding stage. A bypass mechanism useful for any cache following a cache miss is also disclosed. <IMAGE>