发明名称 |
Method for planarization of an integrated circuit |
摘要 |
A method for planarization of an integrated circuit. After a first conducting layer is deposited and patterned, a first insulating layer is deposited over the device. A planarizing layer is then deposited over the integrated circuit and etched back. Portions of the planarizing layer may remain in the lower topographical regions of the first insulating layer to planarize the surface of the device. A second insulating layer is then deposited over the integrated circuit, followed by a third insulating layer. A contact via is formed through the layers to expose a portion of the first conducting layer. A second conducting layer can now be deposited and patterned on the device to make electrical contact with the first conducting layer.
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申请公布号 |
US5485035(A) |
申请公布日期 |
1996.01.16 |
申请号 |
US19930174430 |
申请日期 |
1993.12.28 |
申请人 |
SGS-THOMSON MICROELECTRONICS, INC. |
发明人 |
LIN, YIH-SHUNG;HUANG, KUEI-WU;LU, LUN-TSENG |
分类号 |
H01L21/28;H01L21/302;H01L21/3065;H01L21/3205;H01L21/768;H01L23/522;(IPC1-7):H01L23/48;H01L29/46;H01L29/54;H01L29/62 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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