| 摘要 |
A simple CMOS voltage reference circuit develops a reference voltage from the sum of the threshold voltages of a pair of complementary devices. In a p-type substrate a p-channel device is formed in an isolated n-type well, with the well tied to the source at the reference node. The drain is coupled to the drain of a complementary n-channel device. An additional p-channel device functions as a current source. The voltage reference circuit may be advantageously cascaded to improve stability and insensitivity to the power supply voltage.
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