| 摘要 |
PURPOSE: To prevent analytic work from being complicated by eliminating the need of generating a timewise test for analyzing the timing of a combination theory circuit by transforming a circuit to perform the timing analysis to a functionally equivalent circuit having the same number of level gates. CONSTITUTION: As a starting point, any suitable delay valueδis initially selected (41). A computer transforms a source circuit to a functionally equivalent L path opposite circuit corresponding to the selected delay valueδ(42). In order to find out whether any test effective for the specific value of the delay valueδexists or not, a multiplex fault text is performed (43). When the effective test is found out, the delay of the source circuit isδ(44). When the effective test is not found out, the value ofδis decremented just for certain quantity and that newδis fed back to the step 42 (45). The steps 43 and 45 are repeated until theδis sufficiently reduced, the effective test is found out and the finalδis determined.
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