Method of fabricating a complementary heterojunction FET

摘要

A heterojunction device including a first semiconductive layer on a substrate, a barrier layer on the first layer, a second semiconductive layer on the barrier layer and a multi-layer cap, on the second semiconductive layer. First and second gates positioned on layers of the cap to define first and second transistors, with the cap layers being selected and etched to pin the Fermi level in a first transistor conduction channel in the second semiconductive layer such that the number of carriers in the first conduction channel are substantially less than the number of carriers in surrounding portions of the second semiconductive layer and the Fermi level in a second transistor conduction channel in the first semiconductive layer such that the number of carriers in the second conduction channel are substantially less than the number of carriers in surrounding portions of the first semiconductive layer.