发明名称 SOFTWARE ERROR RELIEF SYSTEM FOR MEMORY BACKUP DEVICE
摘要 PURPOSE:To provide a software error relief system which can easily be realized even in a battery-driven small-sized computer. CONSTITUTION:A parity check circuit 1 is provided as hardware which makes a parity check, and this circuit adds parity data to data when data are stored on a backup memory at the time of power-off, and makes the parity check on read data at the time of power-on and outputs an error detection signal if there is a parity error to report the error to software side. When data are written and read, the software side makes horizontal parity checks to calculate BCC data, and error data are restored on condition that an error is detected only once by the parity check circuit and there only one error bit calculated by XRO calculation based upon the BCC data up to the end of a read of data at the time of the power-on.
申请公布号 JPH07141266(A) 申请公布日期 1995.06.02
申请号 JP19930290190 申请日期 1993.11.19
申请人 FUJITSU KIDEN LTD 发明人 KIHARA ATSUSHI
分类号 G06F12/16;G06F11/10 主分类号 G06F12/16
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