| 摘要 |
PURPOSE:To provide a PLL circuit which can lock a phase in the optimum phase without controlling the loop gain. CONSTITUTION:A PLL circuit 3 is provided with the phase error detecting means 21-29, a loop filter 30 and a VCO 31. Each phase error detecting means adds the offset value to the fixed phase error information when the center frequency of the VCO 31 gets out of a prescribed range set previously. This offset value is given from a free-running counter 24. A sawtooth wave or a triangular wave is applied to the VCO 31 as a control signal. Thus the center frequency of the VCO 31 is set within the prescribed range and then the offset value is added to the phase error information. |
