发明名称 |
Circuit having a master-and-slave and a by-pass |
摘要 |
Because a bypass circuit BP connected in parallel with serial paths of first and second storage circuits MF and SF has less serially-connected stages of gates incorporated therein than the storage circuits and has shorter information transfer delay of input data to an output terminal 21 than the storage circuits, the bypass circuit BP outputs the information to the output terminal before the outputs of the storage circuits are determined when data supplied to a data input terminal 20 is fetched synchronously with a clock signal CK. The first and second storage circuits MF and SF are master/slave-operated in diagnosis mode, and the output operation of the bypass circuit BP is inhibited according to the states of signals C1 and C2 for controlling their master/slave operations regardless of the clock change of the first control signal CK. Thus, the master/slave operations of the first and second storage circuits MF and SF are assured in the diagnosis mode. |
申请公布号 |
US5378934(A) |
申请公布日期 |
1995.01.03 |
申请号 |
US19920991102 |
申请日期 |
1992.12.16 |
申请人 |
HITACHI, LTD. |
发明人 |
TAKAHASHI, TOSHIRO;OHKAWA, MASAAKI;KOIDE, KAZUO |
分类号 |
G01R31/317;G06F11/267;G11C7/10;H03K3/012;H03K3/037;(IPC1-7):H03K3/289;H03K17/56 |
主分类号 |
G01R31/317 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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