| 摘要 |
PURPOSE:To reduce current consumption in the standby state of the bit synchronization circuit and to adopt a high frequency synchronization pulse by generating the synchronization pulse through the synchronization of a phase of a clock of a receiver with a digital signal obtained at a detection output of the radio receiver so as to eliminate a doubled clock frequency. CONSTITUTION:A binary counter 2 is reset by a signal (a) of a pulse width by one clock synchronously with a clock obtained by differentiating a digital signal at a leading/trailing differentiation circuit 1 and a low level or a high level is set for each input of 32 clocks to for a rectangular wave (b). A phase comparator 3 compares the phase of the signal (b) with a phase of a signal of a preset enable binary counter 4 and a signal (c) generated in response to a lead/lag phase is inputted to a 2<1> bit terminal of the binary counter 4 to preset the binary counter 4 and to obtain a desired synchronization pulse. Thus, the standby current is reduced and a high frequency is adopted for the synchronization pulse. |
