| 摘要 |
<p>An asynchronous transfer mode (ATM) switch in which access to a switchcore matrix is monitored and controlled through the logic and buffering functions of switchports connected thereto. The switchcore is greatly simplified by moving the logic and buffering functions to the switchports. The switchcore matrix comprises a plurality of rows, columns, and crosspoints thereof, providing routing paths for the routing of information cells from input points to output points on the matrix. Single-store buffers in the switchcore matrix enable temporary storage and hand-off of individual information cells as they pass through the matrix. The simplicity of the switchcore matrix enables it to be constructed on a single integrated circuit.</p> |
