| 摘要 |
<p>PURPOSE:To solve delay of activation of a signal at the time of transition to multiple selection and non-selection of the signal which is generated at the time of selecting a column address to be substituted and has a function connecting a digit line and an input/output line, in a semiconductor memory circuit of a digit line redundant circuit system. CONSTITUTION:Digit lines D and the inverse of D are connected to first input/ output lines IO and the inverse of IO via a switch SW. Redundant digit lines RD and the inverse of RD are connected to second input/output lines IO' and the inverse of IO' via a switch RSW. The first input/output lines IO and the inverse of IO are connected to read/write circuits 41 and 43 via an input/output line switch circuit IOSW. The second input/output lines IO' and the inverse of IO' are connected to the read/write circuits 41 and 43 via an input/output line switch circuit RIOSW'. Switching from digit lines to redundant digit lines is performed by switching the switch SW and RSW, while switching the input/ output line switch circuit IOSW and RIOSW'.</p> |
