| 摘要 |
<p>PURPOSE:To reset a circuit using plural different clocks even when one clock is stopped, and to reset the circuit by preventing the disturbance of a bus when the clock is operated. CONSTITUTION:When the common clock is operated, and a reset signal is inputted, a synchronization reset means 2a generates a synchronization reset signal synchronizing with the common clock. The synchronization reset signal is applied to a bus side synchronizing circuit 2e, the bus side synchronizing circuit 2e is reset synchronously with the common clock, and the transferring direction of a data transferring direction control means 2c which controls the transferring direction of data between the bus and the module is faced to the module side. Also, when the common clock is stopped, the bus side synchronizing circuit 2e is reset by a signal prepared by the clock in the module, which is outputted from a delay reset means 2b.</p> |
