| 摘要 |
In a total sum calculation circuit for the use in calculating a total sum of first through n-th input data which are represented by a floating point representation and which are composed of first through n-th exponent parts and first through n-th fraction parts, where n is an integer greater than two, an n-input data comparison circuit simultaneously compares the first through the n-th exponent parts with one another to produce a maximum one of the first through the n-th exponent parts and a comparison result signal representative of which one of the first through the n-th exponent parts is the maximum exponent part. Supplied with the first through the n-th exponent parts and the comparison result signal, a shift number calculation circuit calculates first through n-th shift digit numbers between the maximum exponent part and the first through the n-th exponent parts. The first through the n-th fraction parts are shifted by first through n-th shift digit numbers in first through n-th shifters are produced as first through n-th shifted fraction parts which are summed up into an unnormalized fraction part. The unnormalized fraction part is normalized into a total sum fraction part by the use of normalization information derived from the unnormalized fraction part. The maximum exponent part is also normalized by the ( continued) normalization information into a total sum exponent part. A combination of the total sum exponent part and the total sum fraction part is produced as the total sum represented by the floating point representation.
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