发明名称 DATA TRANSMITTING SYSTEM
摘要 PURPOSE:To accelerate processing speed at any one of plural sales data processors. CONSTITUTION:Plural slave side ECR 2 are connected to a master side ECR 1, the master side ECR 1 is provided with a PLU sum-up memory to store the PLU data of all the merchandise to be handled at shops, and the slave side ECR 2 is provided with a PLU sum-up memory to store the PLU data, which are registered more frequently, among the PLU data in the PLU sum-up memory of the master side ECR 1. When a PLU number code is inputted by a bar code reader 4 of the slave side ECR 2, the PLU sum-up memory of the slave side ECR 2 is retrieved and when relevant PLU data are stored, the data are registered and updated. When no data are stored, however, the PLU sum-up memory of the master side ECR 1 is retrieved, and the data are registered and updated. At the time of the settlement of account, the PLU data of the PLU sum-up memory for each slave side ECR 2 are set as the frequently registered PLU data.
申请公布号 JPH05314274(A) 申请公布日期 1993.11.26
申请号 JP19920276827 申请日期 1992.09.22
申请人 CASIO COMPUT CO LTD 发明人 MATSUNAGA HIRONOBU
分类号 G07G1/14;G06F17/40;G06Q30/06;G06Q50/00;G06Q50/10 主分类号 G07G1/14
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