| 摘要 |
A memory device includes first to Sth (S is an integer of 2 or more) memory cell arrays, first to Sth sense amplifier/latch circuits connected to bit lines of these memory cell arrays, and a latch control circuit for inputting and latching data read out from the memory cell arrays to the sense amplifier/latch circuits. In a serial access mode, when a memory cell in the Pth (P is an integer of 1 to S-1) is selected, storage data read out from memory cells belonging to a row of the selected cell in the (P+1)th memory cell array are input and latched to the Pth and (P+1)th sense amplifier/latch circuit by the latch control circuit. When the Sth memory cell array is selected by the access start address, storage data read out from memory cells belonging to a row of the selected cell in the Sth memory cell array and storage data read out from memory cells belonging to a next row of the selected cell in the first memory cell array are input and latched to the Sth and first sense amplifier/latch circuits, respectively. Data latched by the Pth or Sth sense amplifier/latch circuit are read out from the access start address in an order of column addresses, and data latched by the (P+1)th or first sense amplifier/latch circuit are sequentially read out in response to column addresses, respectively.
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