| 摘要 |
<p>PURPOSE:To obtain an extremely small pulse delay circuit which is high in its input impedance and can set arbitrary lag quantity and does not change in its pulse width by providing a phase delay cascaded circuit consisting of a logic inversion circuit and an integration circuit. CONSTITUTION:This pulse delay circuit includes, at least, one phase delay cascaded circuit constituted by cascade-connecting an even number of stages of single-stage phase delay circuits in which the integration circuit consisting of R1, C1 is connected between two inverters G1, G2 by sharing the logic inversion circuit G2 of an output side as the logic inversion circuit of the input side of the phase delay circuit of a following stage. The sum of the lag quantity of the rise time of a pulse by the phase delay circuit of an odd-numbered stage as counting in the order of the passing of the pulse and the lag quantity of the fall time of the pulse by the phase delay circuit of an even-numbered stage is made nearly equal to the sum of the lag quantity of the fall time of the pulse by the phase delay circuit of the odd-numbered state as counting in the order of the passing of the pulse and the lag quantity of the rise time of the pulse by the phase delay circuit of the even-numbered stage.</p> |
