| 摘要 |
The present invention provides a signal delay circuit for substantially steplessly changing a delay interval. The signal delay circuit is composed essentially of a delay controller, a first delay circuit, and a second delay circuit. The delay controller generates and outputs control data consisting of a real number bearing control information for controlling the delay interval, the real number consists of an integral portion and a fractional portion. The first delay circuit receives an incidental signal, delays the incidental signal for creating a first intermediate signal, and outputs the first intermediate signal, the first intermediate signal being delayed with respect to the incidental signal by an interval which is a product of a predetermined cardinal interval and the integral portion of the real number. The second delay circuit receives the first intermediate signal, produces at least one second intermediate signal by delaying the first intermediate signal by at least one interval which is an integral multiple of the predetermined cardinal interval, interpolates the first intermediate signal and said at least one second intermediate signal for producing a delayed signal, and outputs the delayed signal, the delayed signal being delayed with respect to the first intermediate signal by an interval which is a product of the predetermined cardinal interval and the fractional portion of the real number. As a result, the delayed signal is delayed with respect to the incidental signal by a delay interval which is a product of the predetermined cardinal interval and the real number output by the delay control means.
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