| 摘要 |
PURPOSE:To avoid a problem of reduction in synchronization width due to an effect of pseudo synchronization by detecting it that a carrier is in the pseudo synchronization state and stepping out the carrier forcibly, locking the synchronization again and repeating it till the normal synchronization state is reached. CONSTITUTION:Since an output h1 of an error correction word asynchronization detection circuit 17 is at a high level, an output h2 of a carrier asynchronization detection circuit 19 goes to a low level, an output h3 of an inversion circuit 14 goes to a high level, an output of an AND circuit 13 goes to a high level and an input h4 of an intermittent reset generating circuit 22 goes to a high level in the pseudo synchronization state, a high level and a low level are inputted to a flip-flop circuit 15 for each prescribed time. On the other hand, the h1, h2 go both to a low level, the h3 goes to a high level and an output of the intermittent reset generating circuit 22 is fixed to a low level in the normal synchronization state. Thus, since a low level is inputted to the flip-flop circuit 15 in the normal synchronization state, the normal operation is implemented. |
