发明名称 DATA DISCRIMINATOR IN PHASE LOCK OSCILLATION CIRCUIT EMPLOYED IN DATA MEMORY
摘要 PURPOSE:To position a data in the center of a discriminating window at all times regardless of variation of data transfer rate of a data memory. CONSTITUTION:Flip-flop circuits A2-D5 are constituted to output pulses having pulse width of DELTAt+T/2 and DELTAt+3T/2 when the data is shifted by DELTAt from the center of data discriminating window having width T. The flip-flop circuits A2 and D5 are connected, at the output thereof, with lowpass filters A6 and B7 which is further connected with an attenuator 8. An operational amplifier 9 receives outputs from the lowpass filter A6 and the attenuator 8 to produce a differential voltage and charges a capacitor 11 through a switch being controlled by an external signal. Charging voltage of the capacitor 11 is fed back, as a delay voltage control voltage, to a delay circuit 1 which then delays a data pulse (a). According to the constitution, delay time of the delay circuit 1 is controlled to position the data in the center of the data discriminating window regardless of variation of data transfer rate.
申请公布号 JPH05189887(A) 申请公布日期 1993.07.30
申请号 JP19920024549 申请日期 1992.01.14
申请人 NEC CORP 发明人 OKANO YASUSHI
分类号 G11B20/14;H03L7/00 主分类号 G11B20/14
代理机构 代理人
主权项
地址