DUTY ADJUSTING CIRCUIT FOR CLOCK

摘要

PURPOSE:To obtain a clock having optional duty regardless of the duty of an input clock. CONSTITUTION:This circuit is equipped with a flip-flop 2 which outputs a clock (b) from its Q terminal with a clock (a) inputted from a clock input terminal 1 to the CK terminal of the flip-flop 2 and a reset signal (e) inputted from a 2nd delay circuit (B) to the R terminal. Then a clock (c) generated by delaying the clock (b) by a 1st delay circuit (A)3 and inverting the logic by an inverting circuit 4 is inputted to an AND inverting circuit 5 and a differential pulse (d) obtained from the circuit 5 is delayed by a 2nd delay circuit (B)6 and inputted as a reset signal (e) to the R terminal of the flip-flop 2. At this time, the clock having optional duty is outputted to a clock output terminal by selecting the delay quantity of the 2nd delay circuit (B)6.